Clock Reset Generator (Crg); Outline; Features - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

5 Clock Reset Generator (CRG)

This chapter describes the functionality and operation of the Clock Reset Generator (CRG) block.

5.1 Outline

The CRG unit controls the clock and reset signals for the ARM926EJ-S, DDR2 IF, GDC, AHB, and
APB modules. The APIX clock is generated separately (please refer to the APIX chapter for details).

5.2 Features

The CRG block has the following features:
•
Clock Generator
• The internal PLL clock and an external input clock (PLL by-pass mode) can be used
• Main PLL control
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• SSCG control (refer to the SSCG chapter for details and a description of the registers)
• Clock gear control
• The clock frequency of the ARM core and the AXI, AHB and APB busses can be
changed separately
• Control of the clock (Supply/Stop) to the ARM core, AXI, AHB and APB modules
• Reset Generator
• Generation of an internal reset from an external reset signal
• Generation of a software reset
• Input/Output control of the XSRST signal for a JTAG ICE
• Generation of the XTRST (TAP controller reset) signal
• Other Functions
• Watchdog timer function
• Supports the stop mode which halts all the MB86R02 'Jade-D' clocks
PLL oscillation control including stop
PLL oscillation stabilization wait time control
5-1