Channel Priority Control; Fixed Priority - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

15.7.3 Channel priority control

The DMAC controls the priority of each channel using the DMACR/PR bits.

When this priority is set in the DMACR/PR bits, the priority order is fixed and bus usage is

granted to the lowest numbered channel. The priority controller of the DMAC switches the

channel when the active channel enters the transfer gap.

In this way, if all the channels are active at the same time, the lowest numbered channel (ch0)

can be selected by the priority controller to start a transfer. For example, the active channel (ch0)

temporarily loses the bus during the transfer gap. The second lowest numbered channel (ch1) is

then granted bus access. When ch1 loses the bus control during the transfer gap, it is given to

As a result, these 2 channels are able to preferentially acquire bus usage in fixed priority mode.

Figure 15-9 shows the defined channel ordering in fixed priority mode.

HDMAC Internal

Defined channel

Figure 15-9 Defined channel ordering in fixed priority mode