Fujitsu MB86R02 Jade-D Hardware Manual page 784

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MB86R02 'Jade-D' Hardware Manual V1.64

FE flag and BI flag

Operation example of BI flag and of bit 4 and 3 and FE flag in the Line status register (LSR) is

shown in Figure 28-8.

If "L" level is received at the stop bit during reception operation, flaming error occurs and FE flag

becomes "1". The error flag is reset by reading Line status register.

When "L" level continues during transmission time (start bit, data bit, parity bit, and stop bit) for 1

character, break code is detected. These errors are applied to each data in FIFO, and they are

able to be confirmed when CPU reads the first data of FIFO. FE and BI flags are able to be

confirmed in the Status register at reading Line status register whose first data includes framing

and break detection error. Both flags become "0" by reading Status register.

For the case of break detection error, reception data is stored to FIFO as 0.

When break is detected, macro stops reception, and it restarts the process with detecting SIN's

falling edge.

Figure 28-8 Operation example of FE flag and BI flag