Table of Contents
Advertisement
MB86R02 'Jade-D' Hardware Manual V1.64
Bit 5
Polarity2
Pad 2 drive polarity: TTL: 0=normal, 1=inverted; RSDS: 1=normal, 0=inverted
Bit 4
Mode2
Pad 2 drive mode: 0b=differential, 1b=TTL
Bit 1 - 0
Boost2
Boost factor for drive current: x0b=2mA, x1b=4mA (only boost[0] has effect)
DIR_PIN3_CTRL
Register
BaseAddress + 540
H
address
Bit
31 30 29 28 27 26 25 24 23 22 21 20
number
Field
name
R/W
Reset
value
IO Module Pad 3 Control
Bit 20 -
NChanSel3
19
Channel selection for N-Pin of Pad i=3 TTL: 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only)
Bit 18 -
ChanSel3
17
Channel selection for Pad i=3 for RSDS: 00b=channel i, 01b=channel(i-1), 10b=clk, 11b=const0, for TTL: 00b=channel i*2,
01b=channel i*2-1, 10b=clk, 11b=const0
Bit 14
NDelay3
N-pin Padcell 3 delay: 0b=no delay, 1b= half bit clock cycle delay (TTL-mode only)
Bit 13
Delay3
Pad 3 delay: 0b=no delay, 1b= half bit clock cycle delay
Bit 7
InOut3
output enable control, 0b=input enabled, 1b=output enabled
Bit 6
NPolarity3
N-pin of Padcell 3 drive polarity: TTL: 0=normal, 1=inverted; RSDS: no effect
Bit 5
Polarity3
Pad 3 drive polarity: TTL: 0=normal, 1=inverted; RSDS: 1=normal, 0=inverted
Bit 4
Mode3
Pad 3 drive mode: 0b=differential, 1b=TTL
Bit 1 - 0
Boost3
Boost factor for drive current: x0b=2mA, x1b=4mA (only boost[0] has effect)
DIR_PIN4_CTRL
Register
BaseAddress + 544
H
address
Bit
31 30 29 28 27 26 25 24 23 22 21 20
number
Field
name
R/W
Reset
value
IO Module Pad 4 Control
Bit 20 -
NChanSel4
19
Channel selection for N-Pin of Pad i=4 TTL: 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only)
Bit 18 -
ChanSel4
17
Channel selection for Pad i=4 for RSDS: 00b=channel i, 01b=channel(i-1), 10b=clk, 11b=const0, for TTL: 00b=channel i*2,
01b=channel i*2-1, 10b=clk, 11b=const0
Bit 14
NDelay4
N-pin Padcell 4 delay: 0b=no delay, 1b= half bit clock cycle delay (TTL-mode only)
Bit 13
Delay4
Pad 4 delay: 0b=no delay, 1b= half bit clock cycle delay
Bit 7
InOut4
output enable control, 0b=input enabled, 1b=output enabled
Bit 6
NPolarity4
N-pin of Padcell 4 drive polarity: TTL: 0=normal, 1=inverted; RSDS: no effect
Bit 5
Polarity4
Pad 4 drive polarity: TTL: 0=normal, 1=inverted; RSDS: 1=normal, 0=inverted
Bit 4
Mode4
Pad 4 drive mode: 0b=differential, 1b=TTL
Bit 1 - 0
Boost4
Boost factor for drive current: x0b=2mA, x1b=4mA (only boost[0] has effect)
DIR_PIN5_CTRL
Register
BaseAddress + 548
H
address
Bit
31 30 29 28 27 26 25 24 23 22 21 20
number
Field
22-24
19
18
17 16 15
14
NChanSel3 ChanSel3
NDelay3 Delay3
RW
RW
RW
0
0
0
H
H
H
19
18
17 16 15
14
NChanSel4 ChanSel4
NDelay4 Delay4
RW
RW
RW
0
0
0
H
H
H
19
18
17 16 15
14
NChanSel5 ChanSel5
NDelay5 Delay5
13
12 11 10 9 8
7
6
InOut3 NPolarity3 Polarity3 Mode3
RW
RW
RW
0
0
0
H
H
H
13
12 11 10 9 8
7
6
InOut4 NPolarity4 Polarity4 Mode4
RW
RW
RW
0
0
0
H
H
H
13
12 11 10 9 8
7
6
InOut5 NPolarity5 Polarity5 Mode5
5
4
3 2 1
0
Boost3
RW
RW
RW
0
1
0
H
H
H
5
4
3 2 1
0
Boost4
RW
RW
RW
0
1
0
H
H
H
5
4
3 2 1
0
Boost5
Advertisement
Table of Contents
