Timing Diagrams; Display Timing Diagram; Non-Interlace Mode - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

18.8 Timing Diagrams

In the above diagram, VTR, HDP, etc., are the setting values of their associated registers.

The VSYNC/frame interrupt is asserted when display of the last raster ends. When updating

display parameters, synchronize with the frame interrupt so no display disturbance occurs.

Calculation for the next frame is started immediately after the vertical synchronization pulse is

asserted, so the parameters must be updated by the time that calculation is started.

VTR+1 rasters

VSP+1 rasters

VDP+1 rasters

Assert Frame Interrupt

Assert Vsync Interrupt

HDP+1 clocks

HSP+1 clocks

HTP+1 clocks

Non-interlace Timing

VSW+1 rasters

HSW+1 clocks