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MB86R02 'Jade-D' Hardware Manual V1.64
MDC (Multi Display Control)
Register
DisplayBaseAddress + 0x170
address
Bit number
31 30 29 28
Bit field name
MDen
R/W
RW
Initial value
0
This register controls dual display mode.
Bit 0
SC0en0 (screen 0 enable 0)
0:
1:
Bit 1
SC0en1 (screen 0 enable 1)
0:
1:
Bit 5
SC0en5 (screen 0 enable 5)
0:
1:
Bit 6
SC0en6 (screen 0 enable 6)
0:
1:
Bit 7
SC0en7 (screen 0 enable 7)
0:
1:
Bit 8
SC1en0 (screen 1 enable 0)
0:
1:
Bit 9
SC1en1 (screen 1 enable 1)
0:
1:
Bit 13
SC1en5 (screen 1 enable 5)
0:
1:
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0
reserve
R0
0
L0 is not included into screen 0
L0 is included into screen 0
L1 is not included into screen 0
L1 is included into screen 0
L5 is not included into screen 0
L5 is included into screen 0
Cursor0 is not included into screen 0
Cursor0 is included into screen 0
Cursor1 is not included into screen 0
Cursor1 is included into screen 0
L0 is not included into screen 1
L0 is included into screen 1
L1 is not included into screen 1
L1 is included into screen 1
L5 is not included into screen 1
L5 is included into screen 1
SC1en
SC0en
RW
RW
X
X
18-99
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