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MB86R02 'Jade-D' Hardware Manual V1.64
T0STS0
Register address
BaseAddress + 1C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18
Field name
R/W
RWS
Reset value
Channel 0 TX status register 0
Bit 31
Reserved
- 24
Do not modify
Bit 17
Reserved
Do not modify
Bit 10
Reserved
Do not modify
Bit 9
Reserved
Do not modify
Bit 8
Reserved
Do not modify
Bit 7
Reserved
Do not modify
Bit 6
Reserved
Do not modify
Bit 5
Reserved
Do not modify
Bit 4
Reserved
Do not modify
Bit 3
Reserved
Do not modify
Bit 2
Reserved
Do not modify
Bit 1
T0PHYUPRDY
indicates that upstream serial channel (APIX PHY) is operational, While 'PHYUPRDY' is low AShell can't become TA aligned
('CONNECTED' is low). If the local APIX PHY is not used 'PHYUPRDY' is forced to '1' (tx_up_ready).
Bit 0
T0PLLGOOD
pll_good (is the same for all Tx/Rx channels)
T0STS1
Register address
BaseAddress + 20
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Channel 0 TX status register 1
Bit 31 - 24
Reserved
Do not modify
Bit 15 - 8
T0INSYNC
Synchronisation losses tx_up__sync_loss_cnt
Bit 7 - 0
T0PLLBAD
PLL synchronisation losses pll_bad_cnt
R0CFG0
Register address
BaseAddress + 24
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R0_config_byte_4
R/W
Reset value
Channel 0 RX APIX configuration byte 1-4
Bit 31 - 24
R0_config_byte_4
apix config byte, see section 17.4
Bit 23 - 16
R0_config_byte_3
apix config byte, see section 17.4
Bit 15 - 8
R0_config_byte_2
apix config byte, see section 17.4
Bit 7 - 0
R0_config_byte_1
(none)
17-8
H
0
H
H
Reserved
R
0
H
H
R0_config_byte_3
RW
0
H
17
16 15 14 13 12 11
10
R
RWS R R R R R R R R R R
0
0
H
H
T0INSYNC
R0_config_byte_2
RW
RW
86
BC
H
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
H
H
H
H
H
H
H
H
T0PLLBAD
R
R
0
0
H
H
R0_config_byte_1
RW
3D
H
H
0
0
H
H
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