Fujitsu MB86R02 Jade-D Hardware Manual page 256

MB86R02 'Jade-D' Hardware Manual V1.64
(1) PLL lock up time or more Wait
(2) DDRIF macro register setting
Write "5555" to DRIMSD register (offset + 50h)
(3) 166MHz (6[ns]) x 20 cycles = 120[ns] or more Wait
(4) IRESET/IUSRRST release
Write "00000002" to general register 1
(offset + ECh) of CCNT module
(5) 166MHz([ns]) x 20 cycles = 120[ns] or more Wait
(6) IDLLRST release
Write "00000003" to general register 1
(offset + ECh) of CCNT module
(7) DLL LOCK up time (79[µs]) or more Wait
(8) 200[µs] (specification of DDR2SDRAM) or more Wait
(9) MCKE on
Write "003F" to DRIC1 register (offset + 02h)
Write "0000" to DRIC2 register (offset + 04h)
Write "C124" to DRCA register (offset + 06h)
Write "C000" to DRIC register (offset + 00h)
(10) SDRAM initialization
(11) OCD adjustment and ODT setting (CHIP side)
(12) Shift to ODTCONT on (SDRAM side) and DDR2C
normal operation mode
Write "0001" to DROS register (offset + 60h)
Write "4000" to DRIC register (offset + 00h)
Power-on
DRAM initialization completion
Note: For the construction of 512M bit DDR2SDRAM
× 2
Refer to "13.7.2.1 SDRAM Initialization
Procedure" for detail
Refer to "13.7.2.2 OCD Adjustment Procedure"
for detail
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