Clock Control Register (I2Cxccr) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

29.7.4 Clock control register (I2CxCCR)

Address
Bit 31 30 29
Name
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial
valu 0 0 0
e
Bit 7: Unused
The value is always read as '1'.
Bit 6: HSM (High Speed Mode)
This is the standard/high-speed setting bit.
At reading/writing
HSM
0 Standard mode
1 High-speed mode
Bit 5: EN (ENable)
This is the operation permission bit.
At reading/writing
EN
0 Operation is prohibited
1 Operation is permitted
When this bit is "0", each bit of the I2CxBSR register and the I2CxBCR register (excluding the
BER and BEIE bits) is cleared. When the BER bit is set, this bit is cleared.
29-12
ch0：FFF5_6000 + 08h ch1：FFF5_7000 + 08h
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
(Reserved)
R R R R
0 0 0 0
24 23 22 21
(Reserved)
R R R R
0 0 0 0
8 7 6 5
(Reserved) HSM EN
R R R/W R/W R/W R/W R/W R/W R/W
0 1 0 0
State
State
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
CS[4:0]
X X X X
16
R
0
0
X