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MB86R02 'Jade-D' Hardware Manual V1.64
9.6 Operation explanation
It explains the operation of IRC.
9.6.1 Outline of operation
It explains the outline of operation of the interrupt processing enumerating it as an example of the
IRQ24 interrupt.
1. Refer to an instruction vector table address 0000_0080
interrupt is asserted to the ARM core as a result of the decision of priority of the IRQ24
interrupt source by the interrupt controller.
2. Loading instruction LDR PC,[PC,#_0×200] is writed to vector table address 0000_0018
beforehand. The expansion interrupt vector address of IRQ24 (value of the VCT register)
refers to the vector address of IRQ24 in the expansion interrupt vector table by this
instruction for it is possible to certain the load and the ARM core PC.
3. It is necessary to write the branch instruction to the IRQ24 interrupt handler to the expansion
interrupt vector address of IRQ24. The interrupt handler of IRQ24 diverges by this branch
instruction PC. It is necessary to dispose all interrupt handlers within ±32MB of the expansion
interrupt vector table when the branch instruction is used. Use loading instruction LDR
PC,[PC,#_xxx] instead of the branch instruction if the interrupt handler cannot dispose it
within ±32MB.
00000018
LDR PC,[PC, #_0x200]
H
9.6.2 Initialization
Fix an individual exception table after the power-on.
Set the expansion interrupt vector table.
Store loading instruction LDR PC,[PC,#_0×200] to IRQ vector (00000018
Set the base address of the interrupt table to the TBR register.
Set the interrupt level of each interrupt source to the ICR31-00 register.
Set the interrupt level that the IRQ interrupt becomes valid for the ILM register.
Set the flag of the CPSRs register in the ARM core to "0" (IRQ is valid).
Do the interrupt valid according to the IRQM register among the interrupt controllers.
IRQ vector
Reference
FFFFE20
00000018
H
00000018
H
for the ARM core when the IRQ
H
VCT Register
H
Extended interrupt vector table
B IRQ24 Handler
IRQ24 interrupt handler
) in the ARM core.
H
H
9-27
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