Dmac Configuration Examples; Dma Start In Single Channel - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

15.8 DMAC Configuration Examples

Example of block and burst transfer by software request (with DMAC ch0)

(1) Set DMA configuration register

DMACR ← 0x80 (byte writing)

(2) Set DMAC source address register

DMACSA0 ← 0x0000_0000

(3) Set DMAC destination address register

DMACDA0 ← 0x0100_0000

(4) Set DMA configuration B register

DMACB0 ← 0x0808_0000

(5) Set DMA configuration A register

DMACA0 ← 0xA00F_000F

Start DMA transfer

Remark: Setting order of step 1 ~ 4 is arbitrary; however, the one of step 5 is unable to be changed.

• DMA configuration register (DMACR) should be set using byte writes.

• For block and burst transfer by software request, the DMAC configuration A register

(DMACA) should be set last.

DMA transfer is enabled.

Source address is set.

Destination address is set.

Transfer mode, transfer data width, and completion

interrupt are set. In this example, block transfer

mode (MS[1:0] = 0

) is set as transfer mode.

Burst transfer mode is able to be set by MS[1:0] = 1

DMA channel transfer control, software trigger, and

number of block and transfer are set.