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MB86R02 'Jade-D' Hardware Manual V1.64
Bit19-16: WACC (Write Access Cycle)
These bits specify number of cycle required for write access. The address does not
change during the cycle specified in these bits. This value should be larger than the
total number of Address Setup Cycle (WADC) and Write Enable Cycle (WWEC).
When RDY bit is set to "1", the value should be 6 or more (7 cycles or more.)
0, 1
2
|
|
15
Bit15-12: RIDLC (Read Idle Cycle)
These bits set number of idle cycle after read access. They are used to prevent data
collision that occurs by write access immediately after the read access.
0
|
|
15
Bit11-8: FRADC (First Read Address Cycle)
These bits are exclusive use for NOR Flash setting that corresponds to page mode
access, and are set initial latency in the address of Flash read access.
The address is retained with number of cycle specified by these bits only at the first
read access. The subsequent read access is executed according to the number of
cycle set in the RACC. MEM_XCS[0/2/4] and MEM_XRD are asserted
simultaneously.
When other values than 0 are set to these bits, specify "0" to RADC (Read Address
Setup Cycle.)
0
|
|
15
Bit7-4: RADC (Read Address Setup cycle)
These bits set number of read address setup cycle which asserts MEM_XCS[0/2/4]
and its address but not MEM_XRD. When 0 is selected, MEM_XRD and
MEM_XCS[0/2/4] are asserted simultaneously. The specifying value should be within
number of the read access setup cycle.
When NOR Flash page access mode is applied, set these bits to "0".
When RDY bit is set to "1", the value should be 3 or more (3 cycles or more.)
0
|
|
15
Bit3-0: RACC (Read Access Cycle)
These bits set number of cycle required for the read access. Although the address
does not change during the cycle specified by these bits, data is fetched at the last
cycle.
When RDY bit is set to "1", the value should be 3 or more (4 cycles or more.)
0
|
|
11-6
Reserved
3 cycles
16 cycles (initial value)
1 cycle
16 cycles (initial value)
0 cycle (initial value)
15 cycles
0 cycle (initial value)
15 cycles
1 cycle
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