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MB86R02 'Jade-D' Hardware Manual V1.64
17.4 Description of APIX Ashell and APIX PHY configuration bytes
17.4.1 RX
Bit
init
Name
ial
cfg_up_clk_divider[1]
7
0
cfg_up_clk_divider[0]
6
0
reserved
5
1
reserved
4
1
reserved
3
1
reserved
2
1
reserved
1
0
cfg_sbup_smode
0
1
Table 17-2 RX config_byte_1
1
If a setup with the external AShell is used and the external AShell is running with a 62.5 MHz core
clock, then the 62.5MBit/s upstream channel bandwidth for half and low bandwidth mode is not
supported.
17-16
config_byte_1
Description
APIX PHY
upstream channel bandwidth setting
bandwidth mode of downstream link
1000 Mbit/s
00:
not applicable
01:
62.50 MBit/s
10:
41.67 MBit/s
11:
31.25 MBit/s
Note: upstream bandwidth setting has to match
related transmitter device configuration
reserved
APIX PHY
relation of upstream sideband data to core
clock of APIX PHY
0: asynchronous, 1: synchronous
125 MBit/s
500 Mbit/s
62.50 MBit/s
1
31.25 MBit/s
20.83 MBit/s
not applicable
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