Bit Alignment - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

Bit alignment

(1) Transmission word alignment

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

The data written to TXFDAT register from CPU or DMA is written to transmission FIFO after right adjusted.

When transmission is performed with serial bus, word is sent from M bit when CNTREG

to S0CHL and S1CHL) is longer than the word length (set to S0WDL and S1WDL),

remaining bit in the channel becomes CNTREG[MSKB]. If channel length is shorter

than the word's, setting is prohibited.

AB0, AB1, AB2, AB3, AH0, AH1, and AW on the above chart indicate byte 0, byte 1,

byte 2, byte 3, half word 0, half word 1, and word at write accessing to TXFDAT on

Each FB0, FB1, FB2, FB3, FH0, FH1, and FW indicate AB0, AB1, AB2, AB3, AH0,

AH1, and AW are written to transmission FIFO after they are right justified.

Image of CPU written to TXFDAT register

Image of TXFDAT written to FIFO

S0WDL and S1WDL counts to the left from this bit

When S0WDL and S1WDL are 3,

S0WDL and S1WDL are 7,

Figure 27-4 Transmission word line chart

Transmission word