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MB86R02 'Jade-D' Hardware Manual V1.64
Notes for setting registers
Please note the following when setting DMAC registers.
• DMACR, DMACA, DMACB, DMACSA and DMACDA registers are accessible in byte, half-
word, and word sizes.
• Do not set DMAC register address to DMACSA and DMACDA registers.
• Do not change the settings of a channel's register during DMA transfer except the DE/DH
bits of DMACR and the EB/PB bits of DMACA.
Register description format
The following format is used for the description of each register's bits in "15.6.2 DMA
configuration register (DMACR)" to "15.6.6 DMAC destination address register (DMACDAx)".
Address
Bit
31
30
29
Name
R/W
Initial value
Bit
15
14
13
Name
R/W
Initial value
Meaning of item and sign
Address
Address (base address + offset address) of the register
Bit
Bit number of the register
Name
Bit field name of the register
R/W
Attribution of read/write of each bit field
• R0:Read value is always "0"
• R1: Read value is always "1"
• W0: Write value is always "0", and write access of "1" is ignored
• W1: Write value is always "1", and write access of "0" is ignored
• R: Read
• W: Write
Initial value
Each bit field's value after reset
• 0: Value is "0"
• 1: Value is "1"
• X: Value is undefined
Base address + Offset
28
27
26
25
12
11
10
9
24
23
22
21
8
7
6
5
20
19
18
17
4
3
2
1
15-5
16
0
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