Fujitsu MB86R02 Jade-D Hardware Manual page 322

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MB86R02 'Jade-D' Hardware Manual V1.64
R0CFG1
Register address
BaseAddress + 28
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Channel 0 RX APIX configuration byte 5-7
Bit 31 - 24
Reserved
Do not modify
Bit 23 - 16
R0_config_byte_7
apix config byte, see section 17.4
Bit 15 - 8
R0_config_byte_6
apix config byte, see section 17.4
Bit 7 - 0
R0_config_byte_5
(none)
R0CFG2
Register address
BaseAddress + 2C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
Field name
R0_config_byte_shell_4
R/W
Reset value
Channel 0 RX APIX SHELL configuration byte 1-4
Bit 31 - 24
R0_config_byte_shell_4
apix config byte, see section 17.4
Bit 23 - 16
R0_config_byte_shell_3
apix config byte, see section 17.4
Bit 15 - 8
R0_config_byte_shell_2
apix config byte, see section 17.4
Bit 7 - 0
R0_config_byte_shell_1
(none)
R0CTRL
Register address
BaseAddress + 34
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Field name
Reserved
R/W
RWS
Reset value
Channel 0 RX control
Bit
Reserved
31 -
Do not modify
24
Bit 2
R0CFGEN
0: A-Shell and PHY running (write protection on APCFG registers), with falling edge config registers ore overtaken by PHY. 1: (def) A-
Shell and PHY configuration (possible to change APCFG registers), Ashell and PHY (if EnRstToPhy is enabled) is hold in reset, Changes
at configurations bytes (config_byte_*) are allowed only when 'CFGEN' or 'RSTRT' are asserted.
Bit 1
Reserved
Do not modify
R0STS0
Register address
BaseAddress + 38
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18
Field name
R/W
RWS
Reset value
0
H
Channel 0 RX status register 0
Bit 31
Reserved
- 24
Do not modify
H
Reserved
R0_config_byte_7
RWS
0
H
H
R0_config_byte_shell_3
RW
RW
A0
9
H
H
0
H
H
R0_config_byte_6
RW
93
H
R0_config_byte_shell_2
RW
89
H
H
17
16 15 14 13 12 11 10 9
R
R R R R R R R R R R
0
0
0
0
H
H
H
R0_config_byte_5
RW
RW
C0
3F
H
H
6
5
4
3
R0_config_byte_shell_1
RW
0
H
2
1
R0CFGEN
Reserved
RW
RW
1
0
H
8
7
6
5
4
3
2
1
R0PLLGOOD
0
0
0
0
0
0
0
H
H
H
H
H
H
H
H
2
1
0
0
H
0
R
0
H
17-9

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