Interrupt Id Register (Urtxiir) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

28.6.5 Interrupt ID register (URTxIIR)

ch0：FFFE_1000 + 08h ch1：FFFE_2000 + 08h ch2：FFF5_0000 + 08h
Address
ch3：FFF5_1000 + 08h ch4：FFF4_3000 + 08h ch5：FFF4_4000 + 08h
Bit 31 30 29
Name
R/W R R R
Initial value X X X
Bit 15 14 13
Name
R/W R R R
Initial
valu X X X
e
Bit No. Bit name
31:8 Unused
7:6 FIFO1:0
5:4
3:0 ID2:0, NINT
* Bit7:0 = C1h, after the reset
* Numerical value in ( ) is priority level
When character time-out interrupt occurs with having received data, ID2:0, NINT is changed from 0100 to
1100.
Interrupt signal (INTR) is cleared by the following operation.
Priority level:
(1) Read Line status register (LSR)
(2) Read reception FIFO
(3) Read Interrupt ID register (IIR) or write to transmission FIFO
(4) Read Modem status register (MSR)
28-8
28 27 26 25
R R R R
X X X X
12 11 10 9
(Reserved)
R R R R
X X X X
Reserved bit (input "0" at writing)
FIFO status
Fixed to "11"
"00"
Interrupt setting
0001: No interrupt
0110: Reception line status
0100: Reception data existed
1100: Time-out
0010: Transmission FIFO is empty
0000: Modem status
24 23 22 21
(Reserved)
R R R R
X X X X
8 7 6 5
FIFO FIFO
(Reserved)
ST1 ST0
R R R R
X 1 1 0
Function
(1) Top priority
(2)
(2)
(3)
(4)
20 19 18 17
R R R R
X X X X
4 3 2 1
ID2 ID1 ID0 NINT
R R R R
0 0 0 0
16
R
X
0
R
1