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MB86R02 'Jade-D' Hardware Manual V1.64
11.9 Operation
External bus interface equips 3 chip select signals and controls SRAM and Flash.
11.9.1 External bus interface
This interface has 256MB address space that each address is able to be set arbitrarily (actual
max. address size is 32MB with taking bit width of external output address into account.)
Different timing is able to be set to each chip select. NOR Flash is connectable and it accesses
in normal SRAM access.
In SRAM access, MEM_XCS[4/2/0] is selected at 1 access.
When access is performed with wider bit width than the target's, it is converted to continuous
access.
In continuous access, MEM_XCS[4/2/0] is fixed to L and address is changed.
For instance, the case that 32 bit read access is proceeded from internal bus to 16 bit width
device, address is changed from 0 to 2, and the data is continuously fetched from
MEM_ED[15:0] according to the transition timing while MEM_XCS[4/2/0] is fixed to L (refer to
"11.8 Example of access waveform".) Then the data suited to endian is returned to the
internal bus.
When access is proceeded with narrower bit width than the target's (for instance, the byte access
to 16 bit target), byte access is carried out with MEM_XWR[3:0] signal control during writing
operation (for external bus interface, only necessary data is output.)
11.9.2 Low-speed device interface function
The external bus interface has interface function with low-speed device and MEM_RDY pin
which are used by connecting RDY signal to MEM_RDY pin of this LSI. MEM_RDY pin is
available only when wait state is at L and ready state is at H. RDY signal at reading should be
asserted to "L" at least 2 cycles from 2 cycles before falling edge of MEM_XRD signal to actual
falling edge. For the writing operation, the RDY signal should also be asserted to "L" at least 2
cycles from 2 cycles before falling edge of MEM_WXR signal to actual falling edge.
For the access exceeding external data bus width (e.g. word (32 bit) access to 16 bit device), the
access is carried out "Read → Read, Write → Write" continuously until all exceeded bits are
covered.
In this case, MEM_XCS[4/2/0] signal is not negated during the access regardless of setting.
When the device using negation of MEM_XCS[4/2/0] signal, the access should be done within
the target width. For the device without RDY function (e.g. SRAM memory), be sure to set "0"
to RDY bit of applied chip select.
When RDY signal is H from the access start, the access is carried out in the same method as
normal SRAM access.
If RDY becomes L or high pulse during access cycle, the operation is not assured.
* This function cannot be applied to the RDY/BUSY signals of the Flash memory.
11-17
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