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MB86R02 'Jade-D' Hardware Manual V1.64
(none)
T0CFG2
Register address
BaseAddress + C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Channel 0 TX APIX configuration byte 9-11
Bit 31 - 24
Reserved
Do not modify
Bit 23 - 16
T0_config_byte_11
apix config byte, see section 17.4.
Bit 15 - 8
T0_config_byte_10
apix config byte, see section 17.4
Bit 7 - 0
T0_config_byte_9
(none)
T0CFG3
Register address
BaseAddress + 10
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
Field name
T0_config_byte_shell_4
R/W
Reset value
Channel 0 TX APIX SHELL configuration byte1-4
Bit 31 - 24
T0_config_byte_shell_4
apix config byte, see section 17.4
Bit 23 - 16
T0_config_byte_shell_3
apix config byte, see section 17.4
Bit 15 - 8
T0_config_byte_shell_2
apix config byte, see section 17.4
Bit 7 - 0
T0_config_byte_shell_1
(none)
T0CFG4
Register address
BaseAddress + 14
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18
Field name
R/W
Reset value
Channel 0 TX APIX configuration
Bit 17 - 16
T0_DeEmph
Transmit de-emphasis (binary coded, 1LSB = 0.53mA) 00: min 0% 01: 17% 10: 33% 11:max 50%
Bit 15 - 0
T0_CFG4_reserved0
reserved
T0CTRL
Register address
BaseAddress + 18
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Field name
Reserved
R/W
RWS
Reset value
Channel 0 TX control
Bit
Reserved
31 -
Do not modify
24
Bit 2
T0CFGEN
0: A-Shell and PHY running (write protection on APCFG registers), with falling edge config registers ore overtaken by PHY. 1: (def) A-
Shell and PHY configuration (possible to change APCFG registers), Ashell and PHY (if EnRstToPhy is enabled) is hold in reset, Changes
at configurations bytes (config_byte_*) are allowed only when 'CFGEN' or 'RSTRT' are asserted.
Bit 1
Reserved
Do not modify
H
Reserved
T0_config_byte_11
RWS
0
H
H
T0_config_byte_shell_3
RW
RW
0
9A
H
H
H
0
H
T0_config_byte_10
RW
40
H
T0_config_byte_shell_2
RW
A2
H
H
17
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T0_DeEmph
RW
0
H
T0_config_byte_9
RW
RW
2
2
H
H
6
5
4
3
2
T0_config_byte_shell_1
RW
26
H
T0_CFG4_reserved0
RWS
0
H
2
1
T0CFGEN
Reserved
RW
RW
1
0
H
H
1
0
0
17-7
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