Spi Status Register (Spinsr) - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

30.6.5 SPI status register (SPInSR)

This register is to maintain SPI state, and it is not able to be written.

Initial value

Initial value

(Note) This register should be accessed in 32 bit unit

SPI0: FFF4_0000

SPI1: FFF4_5000

Unused bits.

The write access is ignored. The read value of these bits is always "0".

Proper completion of communication between master slaves is indicated.

0 It is under the communication or stand-by (initial value)

1 Communication is completed

SIRQ pin outputs this bit. It is cleared by reading SPISR register.

Figure 30-6 and Figure 30-7 show timing chart.

Unused bits.

The write access is ignored. The read value of these bits is always "0".

Operation error is indicated.

0 Normal operation is in process (initial value)

Prohibited operation occurs

Clear SPE bit of SPI slave control register (SPISCR)

SERR bit is set to "1" by processing other operations than reading SPICR, SPISCR,

and SPISR in the busy state. Moreover, this bit is cleared by changing state to sleep

with clearing SPE bit of SPISCR.

Communication with SPI slave is in process.

It is standing-by (initial value)

It is communicating

SBSY is set to "1" by writing to SPI data register (SPIDR.)

Do not clear SPE bit of SPISCR in the busy state.

This bit is released by either of followings:

SIRQ bit setting

SERR bit setting

Enables/disable SPI unit

0 Disable SPI

1 Enable SPI