Ddr2 Interface Reset Control Register (Cdcrc) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

7.4.17 DDR2 Interface reset control register (CDCRC)

The DDR2 interface unit can be reset by writing a 0 to this register.
The value of the register should be set "1" again in the reset release.
Address
Bit 31 30 29
Name (Reserved)
R/W RW RW RW
Initial value 0 0 0
Bit 15 14 13
Name (Reserved)
R/W RW RW RW
Initial value 0 0 0
Bit field
Number Name
31-2 (Reserved)
1 IRESET
0 IDLLRST
FFF4_2000 + ECh
28 27 26 25
RW RW RW RW
0 0 0 0
12 11 10 9
RW RW RW RW
0 0 0 0
Reserved
Writes are ignored. Reads will return a '0' at all times.
Control IRESET and IUSRRST to the DDR-IF macro.
0 Reset (initial value)
1 No Reset
Control IDLLRST to the DDR-IF macro.
0 Reset (initial value)
1 No Reset
24 23 22 21
RW RW RW RW
0 0 0 0
8 7 6 5
RW RW RW RW
0 0 0 0
Function
20 19 18 17
RW RW RW RW
0 0 0 0
4 3 2 1
IRESET
RW RW RW RW
0 0 0 0
16
RW
0
0
IDLLRS
T
RW
0
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