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MB86R02 'Jade-D' Hardware Manual V1.64
28.6.2 Reception FIFO register (URTxRFR)
ch0：FFFE_1000 + 00h ch1：FFFE_2000 + 00h ch2：FFF5_0000 + 00h
Address
ch3：FFF5_1000 + 00h ch4：FFF4_3000 + 00h ch5：FFF4_4000 + 00h
Bit
31
30
29
Name
R/W
R
R
R
Initial value
X
X
X
Bit
15
14
13
Name
R/W
R
R
R
Initial
valu
X
X
X
e
Bit No.
Bit name
31:8
Unused
7-0
RFR[7:0]
28.6.3 Transmission FIFO register (URTxTFR)
ch0：FFFE_1000 + 00h ch1：FFFE_2000 + 00h ch2：FFF5_0000 + 00h
Address
ch3：FFF5_1000 + 00h ch4：FFF4_3000 + 00h ch5：FFF4_4000 + 00h
Bit
31
30
29
Name
R/W
W
W
W
Initial value
X
X
X
Bit
15
14
13
Name
R/W
W
W
W
Initial
valu
X
X
X
e
Bit No.
Bit name
31:8
Unused
7:0
TFR[7:0]
28-6
(Reading is enabled only at DLAB = 0)
28
27
26
25
R
R
R
R
X
X
X
X
12
11
10
9
(Reserved)
R
R
R
R
X
X
X
X
Reserved bit
This is FIFO register that is able to maintain up to 16 byte. Reception data is
acquired and maintained at the end of reception sequence.
This register is able to proceed system reset as well as reset by FCR bit 1 (RxF
RST.)
RFR register becomes valid at DLAB = 0, and DLL register is assigned at DLAB =
1. RFR
register becomes valid only at reading register, and data is written to
TFR register (at DLAB = 0) or DLL register (at DLAB = 1) according to the setting
value of DLAB when writing.
(Writing is enabled only at DLAB = 0)
28
27
26
25
W
W
W
W
X
X
X
X
12
11
10
9
(Reserved)
W
W
W
W
X
X
X
X
Reserved bit (input "0" at writing)
This is FIFO register that is able to maintain up to 16 byte. Data is maintained in
this register until being transmitted to the Transmission shift register.
This register is able to proceed system reset as well as reset by FCR bit 2 (RxF
RST.)
This register is write only; however, reading operation reads RFR register (at
DLAB = 0) or DLL register (at DLAB = 1) according to setting value of DLAB.
24
23
22
21
(Reserved)
R
R
R
R
X
X
X
X
8
7
6
5
R
R
R
R
X
0
0
0
Function
24
23
22
21
(Reserved)
W
W
W
W
X
X
X
X
8
7
6
5
W
W
W
W
X
0
0
0
Function
20
19
18
17
R
R
R
R
X
X
X
X
4
3
2
1
RFR[7:0]
R
R
R
R
0
0
0
0
20
19
18
17
W
W
W
W
X
X
X
X
4
3
2
1
TFR[7:0]
W
W
W
W
0
0
0
0
16
R
X
0
R
0
16
W
X
0
W
0
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