I2Sxmcr2Reg Register - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

27.6.8 I2SxMCR2REG register

This register is to control enable and disable functions to each channel of sub frame 1.
Address
Bit 31 30 29
S1C S1C S1C
Name
H31 H30 H29
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0
Bit 15 14 13
S1C S1C S1C
Name
H15 H14 H13
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial 0 0 0
Bit field
No. Name
31-0 S1CH31-S1CH00 Name (S1CHxx) of each bit indicates channel number xx of sub frame 1 (e.g. S1CH00
ch0：FFEE_0014 (h)
28 27 26 25
S1C S1C S1C S1C
H28 H27 H26 H25
0 0 0 0
12 11 10 9
S1C S1C S1C S1C
H12 H11 H10 H09
0 0 0 0
bit controls 0th channel of sub frame 1.) Thus, S1CH31 bit controls 31st channel of
sub frame 1. When frame is 1 sub frame construction (SBFN of CNTREG is "0"), this
is invalid.
0 The corresponding channel is disabled
Transmission/Reception are not performed to the disabled channel
1 The corresponding channel is enabled
Transmission/Reception are performed to the enabled channel
24 23 22 21
S1C S1C S1C S1C
H24 H23 H22 H21
0 0 0 0
8 7 6 5
S1C S1C S1C S1C
H08 H07 H06 H05
0 0 0 0
Description
20 19 18 17
S1C S1C S1C S1C
H20 H19 H18 H17
0 0 0 0
4 3 2 1
S1C S1C S1C S1C
H04 H03 H02 H01
0 0 0 0
27-13
16
S1C
H16
0
0
S1C
H00
0