Fujitsu MB86R02 Jade-D Hardware Manual page 26

MB86R02 'Jade-D' Hardware Manual V1.64
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SIG = Signature Unit (signature and checksum calculation for display content, intended for
ASIL)
On-Chip Peripherals
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Unified 32Bit DDR2 memory support 320Mbps (up to 128MB)
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Parallel Flash/SRAM host interface with decryption engine
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CAN (2 channel)
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Media LB (MOST50)
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ADC (4 channel, 10 bit, 1MS/s)
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I2C (2 channel)
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I2S (1 output/input channel)
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PWM (4 channels, extensible up to 8 channels using I/O option)
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Host interface
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SPI Master (2 channels)
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UART (3 channels, extensible up to 6 channels using I/O option)
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GPIO (24 channels)
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APIX I/F (2 channels, 2x Transmitter or 2x Receiver)
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TCON (direct interconnect to column and row drivers via LVTTL or RSDS, smart integration
panel support, smart panel support)
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External Interrupts (4 channels) (the number of channels of the above IO configuration is
tentative)
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Built-in SRAM (2x 32k)
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Hardware Run Length Decompression (RLD)
Clock Generation
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Embedded Spread Spectrum PLL (for reduced EMI)
Input frequency range switchable: 400 MHz ... 700 MHz and 1.0 GHz ... 1.6 GHz
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Modulation Period Delta variable from 0 to 12.5% of the modulation period
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Various modulation types
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Configurable modulation peak and shape
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Embedded oscillator
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