Synchronization Control; Area Allocation; Window Display - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64
- Data formats added from Coral PA are shown shaded.
-  in the rightmost column of the above table indicates that up-scaling capture display is
supported.
- "Unused" above means writing data which is meaningless as image data.The NRGB bit is bit2 of
the VCM register. The other bits are in the CBM register.
Selection of data format of capture image is shown below diagrammatically.
VIS-bit
VI input
0
RGB to
1
YCbCr
RI/GI/BI input
For the ARGB or RGBA formats, use the BLEN bit of the
blend bit to 1 or 0 at pixel write time.
BLEN = 0 (blend bit = 0) (for ARGB, BLEN is MSB; for RGBA, BLEN is LSB)
BLEN = 1 (blend bit = 1) (for ARGB, BLEN is MSB; for RGBA, BLEN is LSB)
18.7.3.2

Synchronization Control

Writes of video image data to the graphics memory and scans in the graphics memory for display are
performed independently. The graphics memory for video captures is managed by a ring buffer
system. It displays one frame while the image data for another frame is being prepared in a memory. If
the frame rate of a video capture differs from that of a display, then the continued ommission of the top
of the display may occur.
18.7.3.3

Area Allocation

An application should allocate an area for about 2.2 frames as the video capture buffer. This area size
is about equivalent to the margin required for frame doublebuffering. Set the start address and the
upper-limit address of the area in the
start position as the upper-limit address.
To allocate n rasters as the video capture buffer, set the upper-limit value as follows:
CBLA = CBOA
In addition, the head addresses of n+1 raster are 64n×CBW and the CBLA+2 raster becomes a buffer
area. For reduced display, allocate the buffer area of the reduced frame size.
18.7.3.4

Window Display

The captured video picture is displayed using L1 layer. The whole or a part captured picture can be
displayed as the whole screen or a window.
When performing the display of captured video data, the L1 layer is configured to capture synchronous
mode (L1CS=1). In this mode, the L1 layer displays the latest frame from a video capture buffer.
Usually, the display address used in this mode is disregarded.
0
YCbCr
to RGB
RGB
1
24 to16
NRGB-bit
CBOA/CBLA
+ 64 (n-2) × CBW
1
ARGB
0
to RGBA
C24-bit
RGBA-bit
CBM register to determine whether to set the
registers. Use this register to specify the raster
CRGB-bit
YCbCr -16 bpp
ARGB - 16bpp
0
ARGB - 24bpp
0
RGBA - 16bpp
1
1
RGBA - 24bpp
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