Notes On Use Of Irc - Fujitsu MB86R02 Jade-D Hardware Manual

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MB86R02 'Jade-D' Hardware Manual V1.64

9.6.6 Notes on use of IRC

The notes on use of IRC is described.

Note concerning IRQ clear timing

When "0" is writed to the IRQF bit of the IRQF register as described in the explanation of "9.5.2 IRQ

flag register (IRQF)", IRQX to the ARM core (interrupt request) is negated. However, after "0" is

writed to IRQF, IRQX is actually negated during one cycle of the APB clock. Therefore, when the

code (interrupt handler) of which it is valid is the interrupt in the ARM core again immediately after "0"

was writed to IRQF is written, the ARM core has the possibility of entering the IRQ mode again by

mistake by IRQX before it is cleared. This has the possibility of occurring when the clock frequency in

the ARM core is especially faster than the frequency of IRC.

To evade this problem, add one dummy instruction (access instruction to the IRC interrupt register)

after IRQF clear instruction. As a result, guarantee for IRQX to be cleared surely before the interrupt

in the ARM core becomes valid again.