Fujitsu MB86R02 Jade-D Hardware Manual page 659

MB86R02 'Jade-D' Hardware Manual V1.64
name
R/W
Reset
value
IO Module Pad 5 Control
Bit 20 - NChanSel5
19 Channel selection for N-Pin of Pad i=5 TTL: 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only)
Bit 18 - ChanSel5
17 Channel selection for Pad i=5 for RSDS: 00b=channel i, 01b=channel(i-1), 10b=clk, 11b=const0, for TTL: 00b=channel i*2,
01b=channel i*2-1, 10b=clk, 11b=const0
Bit 14 NDelay5
N-pin Padcell 5 delay: 0b=no delay, 1b= half bit clock cycle delay (TTL-mode only)
Bit 13 Delay5
Pad 5 delay: 0b=no delay, 1b= half bit clock cycle delay
Bit 7 InOut5
output enable control, 0b=input enabled, 1b=output enabled
Bit 6 NPolarity5
N-pin of Padcell 5 drive polarity: TTL: 0=normal, 1=inverted; RSDS: no effect
Bit 5 Polarity5
Pad 5 drive polarity: TTL: 0=normal, 1=inverted; RSDS: 1=normal, 0=inverted
Bit 4 Mode5
Pad 5 drive mode: 0b=differential, 1b=TTL
Bit 1 - 0 Boost5
Boost factor for drive current: x0b=2mA, x1b=4mA (only boost[0] has effect)
DIR_PIN6_CTRL
Register
BaseAddress + 54C
H
address
Bit
31 30 29 28 27 26 25 24 23 22 21 20
number
Field
name
R/W
Reset
value
IO Module Pad 6 Control
Bit 20 - NChanSel6
19 Channel selection for N-Pin of Pad i=6 TTL : 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only)
Bit 18 - ChanSel6
17 Channel selection for Pad i=6 for RSDS: 00b=channel i, 01b=channel(i-1), 10b=clk, 11b=const0, for TTL: 00b=channel i*2,
01b=channel i*2-1, 10b=clk, 11b=const0
Bit 14 NDelay6
N-pin Padcell 6 delay: 0b=no delay, 1b= half bit clock cycle delay (TTL-mode only)
Bit 13 Delay6
Pad 6 delay: 0b=no delay, 1b= half bit clock cycle delay
Bit 7 InOut6
output enable control, 0b=input enabled, 1b=output enabled
Bit 6 NPolarity6
N-pin of Padcell 6 drive polarity: TTL: 0=normal, 1=inverted; RSDS: no effect
Bit 5 Polarity6
Pad 6 drive polarity: TTL: 0=normal, 1=inverted; RSDS: 1=normal, 0=inverted
Bit 4 Mode6
Pad 6 drive mode: 0b=differential, 1b=TTL
Bit 1 - 0 Boost6
Boost factor for drive current: x0b=2mA, x1b=4mA (only boost[0] has effect)
DIR_PIN7_CTRL
Register
BaseAddress + 550
H
address
Bit
31 30 29 28 27 26 25 24 23 22 21 20
number
Field
name
R/W
Reset
value
IO Module Pad 7 Control
Bit 20 - NChanSel7
19 Channel selection for N-Pin of Pad i=7 TTL: 00b=channel(i*2+1), 01b=channel(i*2), 10b=clk, 11b=const0 (TTL mode only)
Bit 18 - ChanSel7
17 Channel selection for Pad i=7 for RSDS: 00b=channel i, 01b=channel(i-1), 10b=clk, 11b=const0, for TTL: 00b=channel i*2,
01b=channel i*2-1, 10b=clk, 11b=const0
Bit 14 NDelay7
N-pin Padcell 7 delay: 0b=no delay, 1b= half bit clock cycle delay (TTL-mode only)
Bit 13 Delay7
RW RW RW
0 0 0
H H H
19 18 17 16 15 14
NChanSel6 ChanSel6 NDelay6 Delay6
RW RW RW
0 0 0
H H H
19 18 17 16 15 14
NChanSel7 ChanSel7 NDelay7 Delay7
RW RW RW
0 0 0
H H H
RW RW RW
0 0 0
H H H
13 12 11 10 9 8 7 6
InOut6 NPolarity6 Polarity6 Mode6
RW RW RW
0 0 0
H H H
13 12 11 10 9 8 7 6
InOut7 NPolarity7 Polarity7 Mode7
RW RW RW
0 0 0
H H H
RW RW RW
0 1 0
H H H
5 4 3 2 1 0
Boost6
RW RW RW
0 1 0
H H H
5 4 3 2 1 0
Boost7
RW RW RW
0 1 0
H H H
22-25