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MB86R02 'Jade-D' Hardware Manual V1.64
9.5.11 FIQ test register (FIQTEST)
The FIQTEST register controls the test of interrupt controller's IRQ interrupt function.
Address
FFFF_FE00
Bit
31
30
29
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit
15
14
13
Name
-
-
-
R/W
R/W
R/W
R/W
Initial value
X
X
X
Bit field
Number
Name
31-2
-
1
ITEST
0
FTST
9-24
IRC0:
or FFFE_8000
+ 28
H
H
H
28
27
26
25
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
12
11
10
9
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
It is an unused bit.
The write access is ignored. The read value of these bits is undefined.
It is a control bit to test interrupt controller's IRQ interrupt function.
0 The interrupt is not generated with IRQTEST and the FIQTEST register.
The interrupt is generated with the ITST bit of the IRQTEST register and the FTST bit of
1
the FIQTEST register.
Set "0" to the ITEST bit.
This bit is initialized by reset by "0".
It is a control bit to test interrupt controller's IRQ interrupt function.
When the ITEST bit is "1", the FTST bit becomes valid.
0 The interrupt is not generated.
1 The interrupt is generated.
Set "0" to the FTST bit.
This bit is initialized by reset by "0".
IRC1: FFFB_0000
IRC2: FFFB_1000
24
23
22
21
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
8
7
6
5
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
Explanation
+ 28
H
H
+ 28
H
H
20
19
18
17
-
-
-
-
R/W
R/W
R/W
R/W
X
X
X
X
4
3
2
1
-
-
-
ITEST
R/W
R/W
R/W
R/W
X
X
X
0
16
-
R/W
X
0
FTST
R/W
0
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