Fujitsu MB86R02 Jade-D Hardware Manual page 118

MB86R02 'Jade-D' Hardware Manual V1.64
R/W
Reset value
Alternative additional delta to SSCG_PERIOD
Bit 11 SSCG_PERIOD_JITTER
- 0 12 bits for modulation period jitter in PLL clock units, multiplied by a factor of 32. Example: decimal value of 3 means 3 PLL clocks jitter (*32) = 96
(Default value is 10% jitter to 35kHz default modulation period)
SSCG_FSTEP
Register address BaseAddress + 8
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Rising/Falling frequency step on every PLL clock cycle
Bit 31 - 0 SSCG_FSTEP
Frequency step per PLL clock. Default setting is +/-1.5% centre spread
SSCG_FOFFSET
Register address BaseAddress + C
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Two's complement frequency offset to PLL Clock
Bit SSCG_FOFFSET
31 - Two's complement offset of modulation frequency, 00000001: offset = 1, ffffffff offset = -1 0x147A E147 : +1% offset of modulated frequency
0 0x0A3D 70A3 : +0.5% offset of modulated frequency 0xF5C2 8F5D : -0.5% offset of modulated frequency 0xEB85 1EB9 : -1% offset of modulated
frequency
SSCG_IEN
Register address BaseAddress + 14
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Field name
R/W
Reset value
Interrupt Enable Register
Bit 0 IEn_Frequency_Limit
Interrupt enable (enables/disables interrupts using the respective field)
SSCG_InterruptStatus
Register address BaseAddress + 18
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Field name
R/W
Reset value
Interrupt status register
Bit ISts_Frequency_Limit
0 Interrupt status flags, a '1' signifies that the corresponding interrupt condition occurred (even if the interrupt is disabled), writing a '1' clears the flag
(a clear has a higher priority than setting)
SSCG_Status
Register address BaseAddress + 1C
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Field name
R/W
Reset value
Status register
Bit 0 Sts_Frequency_Limit
0: normal operational frequency, 1: maximum frequency exceeded
SSCG_CTRL
H
H
H
H
H
SSCG_FSTEP
RW
209D6
H
SSCG_FOFFSET
RW
0
H
.
RW
3B
H
0
IEn_Frequency_Limit
RW
0
H
0
ISts_Frequency_Limit
RW
0
H
0
Sts_Frequency_Limit
R
0
H
6-5