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MB86R02 'Jade-D' Hardware Manual V1.64
34.5.9
I2S Signal Timing
Table 34-30 Timing Requirements
Signal
Symbol
t
scyc
t
I2S_SCKx
shw
t
slw
t
sfi
I2S_WSx
t
hfi
t
sdi
I2S_SDIx
t
hdi
Table 34-31 Switching Characteristics
Signal
Symbol
t
mcyc
t
I2S_SCKx
mhw
t
mlw
t
I2S_WSx
dfs
t
ddo
I2S_SDOx
t
dfb1
B indicates AHB bus clock frequency.
T indicates I2S_SCKx frequency.
Description
Operating frequency, I2S_SCKx (slave Mode)
Pulse duration, I2S_SCKx High (slave Mode)
Pulse duration, I2S_SCKx Low (slave Mode)
Setup time, external I2S_WSx High before
I2S_SCKx Low
(slave mode)
Hold time, external I2S_WSx High after I2S_SCKx
Low
(slave Mode)
Setup time, I2S_SDIx valid before I2S_SCKx Low
(master mode)
Setup time, I2S_SDIx valid before I2S_SCKx Low
(slave Mode)
Hold time, I2S_SDIx valid after I2S_SCKx Low
(master mode)
Hold time, I2S_SDIx valid after I2S_SCKx Low
(slave mode)
Description
Operating frequency, I2S_SCKx (master mode)
Pulse duration, I2S_SCKx high (master mode)
Pulse duration, I2S_SCKx low (master mode)
Delay time, I2S_SCKx High to I2S_WSx transition
(master mode)
Delay time, I2S_SCKx High to I2S_SDOx valid
except the first bit of transmit frame. (master
mode)
Delay time, I2S_SCKx high to I2S_SDOx valid
except the first bit of transmit frame. (slave mode)
Delay time, I2S_SCKx high to the first bit of a
transmit frame when FSPH bit of I2Sx_CNTREG
register is 1. (master mode)
Value
Min.
Typ.
Max.
–
–
0.5B
0.45T
–
0.55T
0.45T
–
0.55T
6
–
–
0
–
–
8 TODO
–
–
6
–
–
4 TODO
–
–
0
–
–
Value
Min.
Typ.
Max.
–
–
0.5B
0.45T
–
0.55T
0.45T
–
0.55T
-12
–
12
-12
–
17
1
–
6
-14
–
17
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
ns
34-35
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