Fujitsu MB86R02 Jade-D Hardware Manual page 692

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MB86R02 'Jade-D' Hardware Manual V1.64
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Field name
R/W
Reset value
Interrupt status flags, a '1' signifies that the corresponding interrupt condition occurred (even if interrupt is disabled), write '1' clears the flag,
Bit 3
IStsIFfull
Interrupt Status for condition Input FIFO full
Bit 2
IStsIFempty
Interrupt Status for condition Input FIFO empty
Bit 1
IStsError
Interrupt Status for condition AHB Destination access error (info from AHB HRESP)
Bit 0
IStsComplete
Interrupt Status for Condition RLD complete (Target Byte Count reached)
Status
Register address BaseAddress + 2C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
Field name
R/W
Reset value
Status register
Bit 4
Reserved
Bit 3
IFIFOempty
Input FIFO currently empty
Bit 2
OFIFOfull
Output FIFO currently full
Bit 1
IFIFOfull
Input FIFO currently full
Bit 0
Busy
RLD busy
SAHBData
Register address
BaseAddress + 30
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
AHB Slave Input Data
Bit 31 - 0
InData
RLD input data (Data written at this address is is latched into the RLD IFIFO)
Hint: Data is only accepted if register RLDCtrl.AcceptData = 1
TransferCount
Register address
BaseAddress + 34
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Local AHB-master transfer count
Bit 31 - 0
AHBMTransferCount
status count of remaining bytes to transfer during current transaction (decrementing counter)
CurAddress
Register address
BaseAddress + 38
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Local AHB-master transfer Current address
Bit 31 - 0
AHBMCA
Current Destination address
23-8
H
H
H
H
8
7
6 5 4 3
IStsIFfull IStsIFempty IStsError IStsComplete
RW
0
H
Reserved IFIFOempty OFIFOfull IFIFOfull Busy
RWS
0
InData
RW
0
H
AHBMTransferCount
R
0
H
AHBMCA
R
X
2
1
0
RW
RW
RW
0
0
0
H
H
H
3
2
1
0
R
R
R
R
1
0
0
0

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