Interrupt Process And Wait Request Operation To Master; Notes - Fujitsu MB86R02 Jade-D Hardware Manual

Graphics controller

Hide thumbs Also See for MB86R02 Jade-D:

Table of Contents

MB86R02 'Jade-D' Hardware Manual V1.64

Interrupt process and wait request operation to master

When the INT flag of the I2CxBCR register is "H" (when this module generates an interrupt and the

CPU proceeds with an interrupt operation), "L" is output to the SCL line. If the slave side sets "L" on the

SCL line, the master side is unable to generate the next transfer so that slave side performs a wait on

the master side.

System clock and fscl of this module

The supply system clock to this module is within the following range. Communication with a system

clock of 18MHz or more requires a corresponding I2CxCSR setting.

• Master operation: 14MHz ~ 41.5MHz

Set I2CxCCR so that it doesn't exceed the following limits on fscl. If it exceeds the upper limit

of each mode, normal transfer is not executed as it careates a timing violation on the I

Standard: 100kHz

High-speed: 400kHz

• Slave operation: 14MHz ~ 41.5MHz

• Register access: 14MHz ~ 41.5MHz

10 bit slave address

This module does not support a 10 bit slave address. Therefore, do not specify a slave address from

78H to 7BH for the module. If a wrong address is specified, an acknowledge is returned on receiving

1byte however normal transfer will not proceed.

Competition of the SCC, MSS and INT bits

Simultaneous writing to the SCC, MSS, and INT bits causes competition between start and stop

conditions on the next byte transfer. The priority in this case is as follows.

3. Occurrence of the next byte transfer and stop condition

If a "0" is written to the INT bit and the MSS bit simultaneously, the MSS bit is prioritized and

a stop condition occurs.

4. Occurrence of the next byte transfer and start condition

If "0" is written to the INT bit and a "1" is written to the SCC bit simultaneously, the SCC bit is

prioritized and a start condition occurs.

5. Occurrence of start condition and stop condition

Writing a "1" to the SCC bit and "0" to the MSS bit simultaneously is prohibited.

Serial transfer clock setting

If the rising edge delay of the SCL line is large or the clock is expanded for the slave device, the value

may be smaller than the setting value (calculated value) as overhead occurs.