Fujitsu MB86R02 Jade-D Hardware Manual page 651

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MB86R02 'Jade-D' Hardware Manual V1.64
DIR_SMx0Sigs
Register
BaseAddress + 4C8
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
Field name
R/W
Reset value
Sync mixer 0 signal selection
Bit 14 - 12
SMX0SIGS_S4
select 4 000b=const zero,001b=sync sequencer output, 010b...111b sync pulse generator output
Bit 11 - 9
SMX0SIGS_S3
select 3
Bit 8 - 6
SMX0SIGS_S2
select 2
Bit 5 - 3
SMX0SIGS_S1
select 1
Bit 2 - 0
SMX0SIGS_S0
select 0
DIR_SMx0FctTable
Register address
BaseAddress + 4CC
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Sync mixer output = function table [a] a = s4*24+s3*23+s2*22+s1*21+s0*20
Bit 31 - 0
SMXFCT0
Sync mixer 0 function table
DIR_SMx1Sigs
Register
BaseAddress + 4D0
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
Field name
R/W
Reset value
Sync mixer 1 signal selection
Bit 14 - 12
SMX1SIGS_S4
select 4 000b=const zero,001b=sync sequencer output, 010b...111b sync pulse generator output
Bit 11 - 9
SMX1SIGS_S3
select 3
Bit 8 - 6
SMX1SIGS_S2
select 2
Bit 5 - 3
SMX1SIGS_S1
select 1
Bit 2 - 0
SMX1SIGS_S0
select 0
DIR_SMx1FctTable
Register address
BaseAddress + 4D4
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name
R/W
Reset value
Sync mixer output = function table [a] a = s4*24+s3*23+s2*22+s1*21+s0*20
Bit 31 - 0
SMXFCT1
Sync mixer 0 function table
DIR_SMx2Sigs
Register
BaseAddress + 4D8
address
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
Field name
R/W
H
SMX0SIGS_S4 SMX0SIGS_S3 SMX0SIGS_S2 SMX0SIGS_S1 SMX0SIGS_S0
H
H
SMX1SIGS_S4 SMX1SIGS_S3 SMX1SIGS_S2 SMX1SIGS_S1 SMX1SIGS_S0
H
H
SMX2SIGS_S4 SMX2SIGS_S3 SMX2SIGS_S2 SMX2SIGS_S1 SMX2SIGS_S0
13
12
11
10
9
8
7
RW
RW
RW
0
0
0
H
H
SMXFCT0
RW
0
H
13
12
11
10
9
8
7
RW
RW
RW
0
0
0
H
H
SMXFCT1
RW
0
H
13
12
11
10
9
8
7
RW
RW
RW
6
5
4
3
2
1
RW
RW
0
0
H
H
H
6
5
4
3
2
1
RW
RW
0
0
H
H
H
6
5
4
3
2
1
RW
RW
22-17
0
0
0

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