Data Register (I2Cxdar) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

29.7.6 Data register (I2CxDAR)

Address
Bit 31 30 29
Name
R/W R R R
Initial value 0 0 0
Bit 15 14 13
Name
R/W R R R
Initial
valu 0 0 0
e
Bit 7-0: D7-0 (Data 7-0)
This is the serial data storage bit.
This data register is used for serial transfer transmitted from MSB. When data is received (TRX =
0), the data output becomes "1".
This register's writing side is double-buffered so that writing data is loaded to the serial transfer
register on the transmission of each byte if the bus (BB = 1) is in use.
As the serial transfer register is directly read on reading, the received data is only valid if the INT
bit is set.
29-16
ch0：FFF5_6000 + 10h ch1：FFF5_7000 + 10h
28 27 26 25
R R R R
0 0 0 0
12 11 10 9
(Reserved)
R R R R
0 0 0 0
24 23 22 21
(Reserved)
R R R R
0 0 0 0
8 7 6 5
R R/W R/W R/W R/W R/W R/W R/W R/W
0 X X X
20 19 18 17
R R R R
0 0 0 0
4 3 2 1
D[7:0]
X X X X
16
R
0
0
X