Mode Switch Register Like Endian Etc. (Cbsc) - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

7.4.16 Mode switch register like endian etc. (CBSC)

This register is for various mode switches.
Set the endian switch as follows.
wSEL 0 (Little)
HWSWAP - (There is no SWAP. )
WSWAP - (There is no SWAP. )
WSEL:Little/Big switch signal
Hword byte swap switch signal at HWSWAP:Big
Word byte swap switch signal at WSWAP:Big
Address
Bit 31 30 29
Name (Reserved) *1
R/W RW RW RW
Initial value 0 0 0
Bit 15 14 13
Name (Reserved)
R/W RW RW RW
Initial value 0 0 0
*3: VideoCap_performance
*4: AHB2AXI_BIGMODE
Bit field
Number Name
31 (Reserved)
30-28 (Reserved)
27 (Reserved)
26-24 (Reserved)
23 (Reserved)
22-20 SD_Endian
19 (Reserved)
18-16 I2S0_Endian
1 (Big)
Note that only 32 bit access is possible to DDR
memory in big endian mode
0 (There is Swap. )
0 (There is Swap. )
FFF4_2000 + E8h
28 27 26 25
(Reserved) *2
RW RW RW RW
0 0 0 0
12 11 10 9
(Reserv
(Reserved)
ed)
RW RW RW RW
0 0 0 0
Reserved
Writes are ignored. Reads will return a '0' at all times.
Reserved
Writes are ignored. Reads will return a '0' at all times.
Reserved
Writes are ignored. Reads will return a '0' at all times.
The Endian switch of SD is controlled.
Bit 22 wSEL Endian switch 0: Little 1:Big
Bit 21 HWSAP Hword byte swap switch signal at Big
Bit 20 WSWAP Word byte swap switch signal at Big
Reserved
Writes are ignored. Reads will return a '0' at all times.
The Endian switch of I2S0 is controlled.
1(There is no Swap. )
1(There is no Swap. )
24 23 22 21
(Reserved) SD_Endian[2:0]
RW RW RW RW
0 0 0 0
8 7 6 5
(Reserved) (Reserved)
RW RW RW RW
0 0 0 0
Function
20 19 18 17
(Reserv
I2S0_Endian[2:0]
ed)
RW RW RW RW
0 0 0 0
4 3 2 1
(Reserved) *3
RW RW RW RW
0 0 0 0
16
RW
0
0
*4
RW
0
7-25