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MB86R02 'Jade-D' Hardware Manual V1.64
T1CFG4
Register address
BaseAddress + 54
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18
Field name
R/W
Reset value
Channel 1 TX APIX configuration channel 1
Bit 17 - 16
T1_DeEmph
Transmit de-emphasis (binary coded, 1LSB = 0.53mA) 00: min 0% 01: 17% 10: 33% 11:max 50%
Bit 15 - 0
T1_CFG4_reserved0
reserved
T1CTRL
Register address
BaseAddress + 58
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
Field name
Reserved
R/W
RWS
Reset value
Channel 1 TX control
Bit
Reserved
31 -
Do not modify
24
Bit 2
T1CFGEN
0: A-Shell and PHY running (write protection on APCFG registers), with falling edge config registers ore overtaken by PHY. 1: (def) A-
Shell and PHY configuration (possible to change APCFG registers), Ashell and PHY (if EnRstToPhy is enabled) is hold in reset, Changes
at configurations bytes (config_byte_*) are allowed only when 'CFGEN' or 'RSTRT' are asserted.
Bit 1
Reserved
Do not modify
T1STS0
Register address
BaseAddress + 5C
Bit number
31 30 29 28 27 26 25 24 23 22 21 20 19 18
R/W
Reset value
Channel 1 TX status register 0
Bit 31
Reserved
- 24
Do not modify
Bit 17
Reserved
Do not modify
Bit 9
Reserved
Do not modify
Bit 8
Reserved
Do not modify
Bit 7
Reserved
Do not modify
Bit 6
Reserved
Do not modify
Bit 5
Reserved
Do not modify
Bit 4
Reserved
Do not modify
Bit 3
Reserved
Do not modify
Bit 2
Reserved
Do not modify
Bit 1
T1PHYUPRDY
indicates that upstream serial channel (APIX PHY) is operational, While 'PHYUPRDY' is low AShell can't become TA aligned
('CONNECTED' is low). If the local APIX PHY is not used 'PHYUPRDY' is forced to '1' (tx_up_ready).
Bit 0
T1PLLGOOD
pll_good (is the same for all Tx/Rx channels)
17-12
H
H
0
H
H
RWS
0
H
17
16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T1_DeEmph
RW
0
H
17
16 15 14 13 12 11 10 9
R
R
0
0
H
H
T1_CFG4_reserved0
RWS
0
H
2
1
0
T1CFGEN
Reserved
RW
RW
1
0
H
H
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
H
H
H
H
H
H
H
H
H
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