Register Description - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

17.3.4 Register Description

CH0CFG
Register address BaseAddress + 0
Bit number 31 30
Field name
R/W RW RW
Reset value 0 0
H H
Channel 0 Config
Bit CH0ENDwnPhy
31 Enable Downstream PHY, 0=power OFF, 1=Power ON
Bit CH0ENUpPhy
30 Enable Upstream PHY, 0=power OFF, 1=Power ON
Bit CH0SDINCDR_Bw
25 - CDR bandwidth control 000 : no tracking 001 : slowest tracking / lowest bandwidth 3FF : fastest tracking / highest bandwidth
16
Bit CH0SDINWindow
12 - Select window for CDR voter 000: 1 clock (last 4 bits) min 2 edges in any 1 phase 001: 2 clocks (last 8 bits) min 3 edges in any 1 phase
10 010: 3 clocks (last 12 bits) min 3 edges in any 1 phase 011: 4 clocks (last 16 bits) min 3 edges in any 1 phase 100: until 2 edges received
in any one phase 101: until 4 edges received in any one phase 110: until 8 edges received in any one phase 111: until 16 edges received
in any one phase
Bit 9 CH0SDIN_Invert
1: Invert data on SDIN pin (PCB optimization)
Bit 8 CH0SDOUT_Invert
1: Invert data on SDOUT pin (PCB optimization)
Bit 6 CH0UpNomSwing
- 3 Transmit swing (binary coded, 1 LSB = 0.53mA) 0000: min 4mA, 0001: 4.53mA, ..., 1111: max 12mA,
Bit 2 Reserved
Do not modify
Bit 1 Reserved
- 0 Do not modify
T0CFG0
Register address BaseAddress + 4
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name T0_config_byte_4
R/W
Reset value
Channel 0 TX APIX configuration byte 1-4
Bit 31 - 24 T0_config_byte_4
apix config byte, see section 17.4
Bit 23 - 16 T0_config_byte_3
apix config byte, see section 17.4
Bit 15 - 8 T0_config_byte_2
apix config byte, see section 17.4
Bit 7 - 0 T0_config_byte_1
(none)
T0CFG1
Register address BaseAddress + 8
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field name T0_config_byte_8
R/W
Reset value
Channel 0 TX APIX configuration byte 5-8
Bit 31 - 24 T0_config_byte_8
apix config byte, see section 17.4
Bit 23 - 16 T0_config_byte_7
apix config byte, see section 17.4
Bit 15 - 8 T0_config_byte_6
apix config byte, see section 17.4
Bit 7 - 0 T0_config_byte_5
17-6
H
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RW
100
H
H
T0_config_byte_3
RW
91
H
H
T0_config_byte_7
RW
12
H
9
RW RW
6 0
H H
T0_config_byte_2
RW RW
0 FE
H
T0_config_byte_6
RW RW
C7 33
H
8 7 6 5 4 3 2 1
Reserved Reserved
RW RW RW RW
0 F 0 1
H H H
T0_config_byte_1
RW
F0
H H
T0_config_byte_5
RW
24
H H
0
H