Fujitsu MB86R02 Jade-D Hardware Manual page 786

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MB86R02 'Jade-D' Hardware Manual V1.64

Operation example of OE flag of bit 1 in the Line status register (LSR) is shown in Figure 28-10.

APB r eadi ng

When next character is received completely to the Reception shift register in the status that

reception FIFO is full, overrun error occurs. In this case, OE flag of the Line status register is set

immediately and interrupt occurs (if it is permitted.)

Operation example of DR flag of bit 0 in the Line status register (LSR) is shown in Figure 28-11.

M ar k st at e

r egi st er readi ng

When reception data is received and 1 byte or more of data is stored in reception FIFO, DR flag of

the Line status register becomes "1". The flag becomes "0" by reading reception FIFO data and

FIFO becomes empty.

When error (parity, break detection, and flaming) is included in the data stored in reception FIFO,

ERRF flag of bit 7 of the Line status register (LSR) is set to "1" during reception operation.

If there is no error data in FIFO except the one set ERRF flag when CPU reads the register, this

flag is cleared to "0".

Li ne st at us

Figure 28-10 Operation example of OE flag

1 char act er

Figure 28-11 Operation example of DR flag

Par i t y bi t