Fujitsu MB86R02 Jade-D Hardware Manual page 178

MB86R02 'Jade-D' Hardware Manual V1.64
Address
Base Offset
+ 78 Interrupt control register 18
H
+ 7C Interrupt control register 19
H
+ 80 Interrupt control register 20
H
+ 84 Interrupt control register 21
H
+ 88 Interrupt control register 22
H
+ 8C Interrupt control register 23
H
+ 90 Interrupt control register 24
H
+ 94 Interrupt control register 25
H
+ 98 Interrupt control register 26
H
+ 9C Interrupt control register 27
H
+ A0 Interrupt control register 28
H
+ A4 Interrupt control register 29
H
+ A8 Interrupt control register 30
H
+ AC Interrupt control register 31
H
9-10
Register name Abbreviation
ICR18
ICR19
ICR20
ICR21
ICR22
ICR23
ICR24
ICR25
ICR26
ICR27
ICR28
ICR29
ICR30
ICR31
Explanation
The level of the IRQ18 interrupt is set (DMAC ch.2
interrupt).
The level of the IRQ19 interrupt is set (DMAC ch.3
interrupt).
The level of the IRQ20 interrupt is set (DMAC ch.4
interrupt).
The level of the IRQ21 interrupt is set (DMAC ch.5
interrupt).
The level of the IRQ22 interrupt is set (DMAC ch.6
interrupt).
The level of the IRQ23 interrupt is set (DMAC ch.7
interrupt).
The level of the IRQ24 interrupt is set (UART ch.0
interrupt).
The level of the IRQ25 interrupt is set (UART ch.1
interrupt).
The level of the IRQ26 interrupt is set (unused and
access prohibited).
The level of the IRQ27 interrupt is set (unused and
access prohibited).
The level of the IRQ28 interrupt is set (unused and
access prohibited).
The level of the IRQ29 interrupt is set (unused and
access prohibited).
The level of the IRQ30 interrupt is set (unused and
access prohibited).
The level of the IRQ31 interrupt is set (unused and
access prohibited).