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Epson Research and Development
Vancouver Design Center
MOD Rate Register
REG[11h]
n/a
7
6
bits 5-0
Horizontal Total Register
REG[12h]
n/a
7
6
bits 6-0
Note
Horizontal Display Period Register
REG[14h]
n/a
7
6
bits 6-0
Note
Hardware Functional Specification
Issue Date: 01/11/13
5
MOD Rate Bits [5:0]
These bits are for passive LCD panels only.
When these bits are all 0, the MOD output signal (DRDY) toggles every FPFRAME.
For a non-zero value n, the MOD output signal (DRDY) toggles every n FPLINE.
5
Horizontal Total Bits [6:0]
These bits specify the LCD panel Horizontal Total period, in 8 pixel resolution. The Hori-
zontal Total is the sum of the Horizontal Display period and the Horizontal Non-Display
period. Since the maximum Horizontal Total is 1024 pixels, the maximum panel resolu-
tion supported is 800x600.
Horizontal Total in number of pixels = ((REG[12h] bits 6:0) + 1) × 8
1
This register must be programmed such that the following formulas are valid.
HDPS + HDP < HT
2
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Inter-
face" on page 56.
5
Horizontal Display Period Bits [6:0]
These bits specify the LCD panel Horizontal Display Period (HDP), in 8 pixel resolution.
The Horizontal Display Period should be less than the Horizontal Total to allow for a suf-
ficient Horizontal Non-Display Period.
Horizontal Display Period in number of pixels = ((REG[14h] bits 6:0) + 1) × 8
For passive panels, HDP must be a minimum of 32 pixels and can be increased by mul-
tiples of 16. For TFT panels, HDP must be a minimum of 16 pixels and can be increased
by multiples of 8.
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface"
on page 56.
MOD Rate Bits 5-0
4
3
Horizontal Total Bits 6-0
4
3
Horizontal Display Period Bits 6-0
4
3
Read/Write
2
1
Read/Write
2
1
Read/Write
2
1
X31B-A-001-08
Page 103
0
0
0
S1D13706
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