Table 6-23: Tft A.c. Timing - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
FPFRAME cycle time
t1
FPFRAME pulse width low
t2
FPFRAME falling edge to FPLINE falling edge phase difference
t3
FPLINE cycle time
t4
FPLINE pulse width low
t5
FPLINE Falling edge to DRDY active
t6
DRDY pulse width
t7
t8 DRDY falling edge to FPLINE falling edge
t9 FPSHIFT period
t10 FPSHIFT pulse width high
t11 FPSHIFT pulse width low
t12 FPLINE setup to FPSHIFT falling edge
t13 DRDY to FPSHIFT falling edge setup time
t14 DRDY hold from FPSHIFT falling edge
t15 Data setup to FPSHIFT falling edge
t16 Data hold from FPSHIFT falling edge
1. Ts = pixel clock period
2. t6min = HDPS - HPS
3. t8min = HPS - (HDP + HDPS)
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-23: TFT A.C. Timing

Parameter
if negative add HT
if negative add HT
Min Typ Max
VT
VPW
HPS
HT
HPW
note 2 250
HDP
note 3
1
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Page 75
Units
Lines
Lines
Ts (note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
S1D13706
X31B-A-001-08