Table 7-4: Relationship Between Mclk And Pclk; Table 7-5: Pwmclk Clock Selection; Pwmclk - Epson S1D13706 Technical Manual

Page 92

7.1.4 PWMCLK

S1D13706
X31B-A-001-08
There is a relationship between the frequency of MCLK and PCLK that must be
maintained.

Table 7-4: Relationship between MCLK and PCLK

SwivelView Orientation
SwivelView 0° and 180°
SwivelView 90° and 270°
PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel.
The source clock options for PWMCLK may be selected as in the following table.
Source Clock Options
For further information on controlling PWMCLK, see Section 8.3.9, "Pulse Width
Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers" on
page 126.
Note
The S1D13706 provides Pulse Width Modulation output on the pin PWMOUT.
PWMOUT can be used to control LCD panels which support PWM control of the back-
light inverter.
Color Depth (bpp) MCLK to PCLK Relationship
16
8
4
2
1
16/8/4/2/1

Table 7-5: PWMCLK Clock Selection

PWMCLK Selection
CLKI REG[B1h] bit 0 = 0
CLKI2 REG[B1h] bit 0 = 1
Epson Research and Development
Vancouver Design Center
≥ f
f
MCLK PCLK
÷
≥ f
f 2
MCLK PCLK
÷
≥ f
f 4
MCLK PCLK
÷
≥ f
f 8
MCLK PCLK
÷
≥ f
f 16
MCLK PCLK
≥ 1.25f
f
MCLK PCLK
Hardware Functional Specification
Issue Date: 01/11/13