Epson S1D13706 Technical Manual page 271

Epson Research and Development
Vancouver Design Center
13706CFG Configuration Program
Issue Date: 01/03/29
The S1D13706 may use as many as two input clocks or as few as one. The more clocks used
the greater the flexibility of choice in display type and memory speed.
CLKI
CLKI2
PCLK
Source
Divide
Timing
This setting determines the frequency of CLKI.
Select "Auto" to have the CLKI frequency determined
automatically based on settings made on other configu-
ration tabs. After completing the other configurations,
the required CLKI frequency will be displayed in blue
in the Auto section.
If the system design requires the CLKI frequency to be
fixed at a particular rate, set this value by selecting a
preset frequency from the drop down list or entering the
desired frequency in MHz.
This setting determines the frequency of CLKI2.
Select "Auto" to have the CLKI2 frequency determined
automatically based on settings made on other configu-
ration tabs. After completing the other configurations,
the required CLKI2 frequency will be displayed in blue
in the Auto section.
If the system design requires the CLKI2 frequency to be
fixed at a particular rate, set this value by selecting a
preset frequency from the drop down list or entering the
desired frequency in MHz.
These settings select the clock signal source and divisor
for the pixel clock (PCLK).
Selects the PCLK source. Possible sources include
CLKI, CLKI2, BCLK or MCLK.
Specifies the divide ratio for the clock source signal.
The divide ratio is applied to the PCLK source to derive
PCLK.
Selecting "Auto" for the divisor allows the configu-
ration program to calculate the best clock divisor.
Unless a very specific clocking is being specified, it is
best to leave this setting on "Auto".
This field shows the actual PCLK used by the configu-
ration process.
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S1D13706
X31B-B-001-03