Epson S1D13706 Technical Manual page 171

Epson Research and Development
Vancouver Design Center
Note
Value Value
Register
(Hex) (Binary)
04h 00 0000 0000
05h 43 0100 0011
10h D0 1101 0000
11h 00 0000 0000
12h 2B 0010 1011
14h 27 0010 0111
16h 00 0000 0000
17h 00 0000 0000
18h FA 1111 1010
19h 00 0000 0000
1Ch EF 1110 1111
1Dh 00 0000 0000
1Eh 00 0000 0000
1Fh 00 0000 0000
20h 87 1000 0111
22h 00 0000 0000
23h 00 0000 0000
24h 80 1000 0000
26h 01 0000 0001
27h 00 0000 0000
Programming Notes and Examples
Issue Date: 01/02/23
The following table represents the sequence and values written to the S1D13706 registers
to control a configuration with these specifications.
• 320x240 color single passive LCD @ 70Hz.
• 8-bit data interface, format 2.
• 8 bit-per-pixel (bpp) color depth - 256 colors.
• 50MHz input clock for CLKI.
• MCLK = BCLK = CLKI = 50MHz.
• PCLK = CLKI ÷ 8 = 6.25MHz.
On the S5U13706B00C evaluation board, CNF[7:6] must be set to 00.
Table 2-1: Example Register Values
Clock Configuration (MCLK, BCLK, PCLK)
Sets BCLK to MCLK divide to 1:1
Sets PCLK = (PCLK source ÷ 8) and the PCLK source = CLKI2
Panel Setting Configuration
Selects the following:
• panel data format = 2
• color/mono panel = color
• panel data width = 8-bit
• active panel resolution = don't care
• panel type = STN
MOD rate = don't care
Sets the horizontal total
Sets the horizontal display period
Sets the horizontal display period start position
Sets the vertical total
Sets the vertical display period
Sets the vertical display period start position
Sets the FPLINE pulse polarity and FPLINE pulse width
Sets the FPLINE pulse start position
Sets the FPFRAME pulse polarity and FPFRAME pulse width
Sets the FPFRAME pulse start position
Description
Page 11
Notes
S1D13706
X31B-G-003-03