Host Bus Interface Signals - Epson S1D13706 Technical Manual

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3.2 Host Bus Interface Signals

S1D13706
X31B-G-010-02
The Host Bus Interface requires the following signals.
• CLKI is a clock input which is required by the S1D13706 Host Bus Interface as a source
for its internal bus and memory clocks. This clock is typically driven by the host CPU
system clock. For this example, BCLK0 from the Motorola MCF5307 is used for CLKI.
• The address inputs AB[16:0] connect directly to the MCF5307 address bus (A[16:0]).
• DB[7:0] connects D[23:16] (the MCF5307 low order byte). DB[15:8] connects to
D[31:24] (the MCF5307 high order byte). CNF4 must be set to select big endian mode.
• Chip Select (CS#) must be driven low by CS4 whenever the S1D13706 is accessed by
the Motorola MCF5307.
• M/R# (memory/register) selects between memory or register accesses. This signal may
be connected to an address line, allowing system address A17 to be connected to the
M/R# line.
• WE0# connects to BWE0 (the low byte enable signal from the MCF5307) and must be
driven low when the MCF5307 is writing the low byte to the S1D13706.
• WE1# connects to BWE1 (the high byte enable signal from the MCF5307) and must be
driven low when the MCF5307 is writing the high byte to the S1D13706.
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively.
Both signals are driven low by OE when the Motorola MCF5307 is reading data from
the S1D13706.
• WAIT# connects to TA and is a signal which is output from the S1D13706 that indi-
cates the host CPU must wait until data is ready (read cycle) or accepted (write cycle) on
the host bus. Since host CPU accesses to the S1D13706 may occur asynchronously to
the display update, it is possible that contention may occur in accessing the S1D13706
internal registers and/or refresh memory. The WAIT# line resolves these contentions by
forcing the host to wait until the resource arbitration is complete. This signal is active
low and may need to be inverted if the host CPU wait state signal is active high.
• The Bus Status (BS#) signal is not used in the bus interface for Generic #1 mode and
must be tied high to HIO V .
DD
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/23