Gcp Data Signal; Gcp Data Structure - Epson S1D13706 Technical Manual

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5 GCP Data Signal

5.1 GCP Data Structure

GCP index 00h
GCP data register window
b7
b6 b5
...
0 1 2
...
1 1
0
GCP
falling edge
of RES
Connecting to the Epson D-TFD Panels
Issue Date: 01/02/23
The D-TFD panel uses a 256-bit bit chain to control the pixel/FPSHIFT (XSCL) positions
relative to the falling edge of the GPIO4 (RES) signal. A one in each bit indicates the
presence of a GCP pulse at that pixel/XSCL position. A zero indicates the absence of a GCP
pulse. For D-TFD AC Timing required by the S1D13706, see the S1D13706 Hardware
Functional Specification, document number X31B-A-001-xx.
The S1D13706 uses two registers to program the GCP Data:
• D-TFD GCP Index Register (REG[28h]
• D-TFD GCP Data Register (REG[2Ch])
The 256-bit GCP data is organized into 32 8-bit data registers, each addressable by the D-
TFD GCP Index register (REG[28h]).
GCP index 01h
GCP data register window
b0 b7
GCP bit chain
7 8
1 0
Figure 5-1: GCP Data
GCP index 1Fh
GCP data register window
b0 b7
Page 19
b0
...
256
...
0
S1D13706
X31B-G-012-03