Table 8-16: Cv Pulse Control - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
bit 3 and bit 0
Bit 3
0
0
1
x = don't care
Note
bit 2
bit 1
Note
bit 0
Hardware Functional Specification
Issue Date: 01/11/13
CV Pulse Force High (bit 3) and CV Pulse Enable (bit 0)
These bits control the CVOUT pin and CV Pulse circuitry as follows.

Table 8-16: CV Pulse Control

Bit 0
1
0
x
When CVOUT is forced low or forced high it can be used as a general purpose output.
1
Bit 3 must be set to 0 and bit 0 must be set to 1 before initiating a new burst using the
CV Pulse Burst Start bit.
2
The CV Pulse circuitry is disabled when Power Save Mode is enabled.
CV Pulse Burst Status
This is a read-only bit. A "1" indicates a CV pulse burst is occurring. A "0" indicates no
CV pulse burst is occurring. Software should wait for this bit to clear before starting
another burst.
CV Pulse Burst Start
A 1 in this bit initiates a single CVOUT pulse burst. The number of clock pulses generated
is programmable from 1 to 256. The frequency of the pulses is the divided CV Pulse
source divided by 2, with 50/50 duty cycle. This bit should be cleared to 0 by software
before initiating a new burst.
This bit has effect only if the CV Pulse Enable bit is 1.
CV Pulse Enable
See description for bit 3.
Result
CV Pulse circuitry enabled
(controlled by REG[B1h] and REG[B2h])
CVOUT forced low
CVOUT forced high
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S1D13706
X31B-A-001-08