Epson Research and Development
Vancouver Design Center
REDCAP2
BUS
A[21:17]
CSn
A[16:1]
D[15:0]
R/W
OE
EB1
EB0
CLK
RESET_OUT
*Note: CSn# can be any of CS0-CS4
MC68EZ328/
MC68VZ328
DragonBall
BUS
A[25:17]
CSX
A[16:1]
D[15:0]
LWE
UWE
OE
DTACK
CLKO
RESET
Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 "DragonBall" Bus)
Hardware Functional Specification
Issue Date: 01/11/13
HIOVDD
BS#
M/R#
Decoder
CS#
AB[16:1]
DB[15:0]
RD/WR#
RD#
WE0#
WE1#
CLKI
RESET#
AB0
VSS
Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus)
HIOVDD
BS#
RD/WR#
M/R#
Decoder
CS#
AB[16:1]
DB[15:0]
WE0#
WE1#
RD#
WAIT#
CLKI
RESET#
AB0
VSS
.
Oscillator
S1D13706
.
Oscillator
S1D13706
FPDAT[7:4]
D[3:0]
FPSHIFT
FPSHIFT
FPFRAME
FPFRAME
FPLINE
FPLINE
DRDY
MOD
GPO
FPDAT[7:0]
D[7:0]
FPSHIFT
FPSHIFT
FPFRAME
FPFRAME
FPLINE
FPLINE
DRDY
MOD
GPO
X31B-A-001-08
Page 17
4-bit
Single
LCD
Display
8-bit
Single
LCD
Display
S1D13706