Table of Contents
Advertisement
Page 106
Vertical Display Period Start Position Register 0
REG[1Eh]
7
6
Vertical Display Period Start Position Register 1
REG[1Fh]
7
6
bits 9-0
FPLINE Pulse Width Register
REG[20h]
FPLINE Pulse
Polarity
7
6
bit 7
bits 6-0
S1D13706
X31B-A-001-08
Vertical Display Period Start Position Bits 7-0
5
n/a
5
Vertical Display Period Start Position Bits [9:0]
These bits specify the Vertical Display Period Start Position for panels in 1 line resolution.
For passive LCD panels these bits must be set to 00h.
For TFT panels, VDPS is calculated using the following formula.
VDPS = (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0)
Note
1
This register must be programmed such that the following formula is valid.
VDPS + VDP < VT
2
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Inter-
face" on page 56.
5
FPLINE Pulse Polarity
This bit selects the polarity of the horizontal sync signal. For passive panels, this bit must
be set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the
panel (typically FPLINE or LP).
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
FPLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. The
horizontal sync signal is typically FPLINE or LP, depending on the panel type.
FPLINE Pulse Width in number of pixels = (REG[20h] bits 6:0) + 1
Note
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Inter-
face" on page 56.
4
3
4
3
FPLINE Pulse Width Bits 6-0
4
3
Epson Research and Development
Vancouver Design Center
Read/Write
2
1
Read/Write
Vertical Display Period Start
Position Bits 9-8
2
1
Read/Write
2
1
Hardware Functional Specification
Issue Date: 01/11/13
0
0
0
Advertisement
Chapters
Table of Contents
