Table 6-16: Panel Timing Parameter Definition And Register Summary - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
Symbol
HT Horizontal Total
1
HDP Horizontal Display Period
HDPS Horizontal Display Period Start Position
HPS FPLINE Pulse Start Position
HPW FPLINE Pulse Width
VT Vertical Total
VDP Vertical Display Period
VDPS Vertical Display Period Start Position
VPS FPFRAME Pulse Start Position
VPW FPFRAME Pulse Width
1. For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16.
For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8.
2. The following formulas must be valid for all panel timings:
HDPS + HDP < HT
VDPS + VDP < VT
Hardware Functional Specification
Issue Date: 01/11/13

Table 6-16: Panel Timing Parameter Definition and Register Summary

Description
1
Derived From
((REG[12h] bits 6-0) + 1) x 8
((REG[14h] bits 6-0) + 1) x 8
For STN panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 22)
For TFT panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 5)
(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
(REG[20h] bits 6-0) + 1
(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1
(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1
REG[1Fh] bits 1-0, REG[1Eh] bits 7-0
REG[27h] bits 1-0, REG[26h] bits 7-0
(REG[24h] bits 6-0) + 1
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Units
Ts
Lines (HT)
S1D13706
X31B-A-001-08